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Platform Flash In-System Programmable Configuration PROMs
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DS123 (v2.1) November 18, 2003
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Preliminary Product Specification
Features
* * * * * * * * * In-System Programmable PROMs for Configuration of Xilinx FPGAs Low-Power Advanced CMOS FLASH Process Endurance of 20,000 Program/Erase Cycles Operation over Full Industrial Temperature Range (-40C to +85C) Available in small footprint packages: VO20, VO48, and FS48 IEEE Standard 1149.1/1532 Boundary-Scan (JTAG) Support for Programming, Prototyping, and Testing JTAG Command Initiation of Standard FPGA Configuration Cascadable for Storing Longer or Multiple Bitstreams Dedicated Boundary-Scan (JTAG) I/O Power Supply (VCCJ) * * * I/O Pins Compatible with Voltage Levels Ranging From 1.5V to 3.3V Design Support Using the Xilinx Alliance ISE and Foundation ISE Series Software Packages XCF01S/XCF02S/XCF04S - 3.3V supply voltage - Serial FPGA configuration interface XCF08P/XCF16P/XCF32P - 1.8V supply voltage - Serial or parallel FPGA configuration interface - Design revision technology enables storing and accessing multiple design revisions for configuration - Built-in data decompressor compatible with Xilinx advanced compression technology
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Table 1: Platform Flash PROM Features
Density VCCINT VCCO / VCCJ Range Packages JTAG ISP Programming Serial Configuration Parallel Configuration Design Revisioning Compression
XCF01S XCF02S XCF04S XCF08P XCF16P XCF32P
1 Mbit 2 Mbit 4 Mbit 8 Mbit 16 Mbit 32 Mbit
3.3V 3.3V 3.3V 1.8V 1.8V 1.8V
1.8V - 3.3V 1.8V - 3.3V 1.8V - 3.3V 1.5V - 3.3V 1.5V - 3.3V 1.5V - 3.3V
VO20 VO20 VO20 VO48 FS48 VO48 FS48 VO48 FS48

Description
Xilinx introduces the Platform Flash series of in-system programmable configuration PROMs. Available in 1 to 32 Megabit (Mbit) densities, these PROMs provide an easy-to-use, cost-effective, and reprogrammable method for storing large Xilinx FPGA configuration bitstreams. The Platform Flash PROM series includes both the 3.3V XCFxxS PROM and the 1.8V XCFxxP PROM. The XCFxxS version includes 4-Mbit, 2-Mbit, and 1-Mbit PROMs that support Master Serial and Slave Serial FPGA configuration modes (Figure 1). The XCFxxP version includes 32-Mbit, 16-Mbit, and 8-Mbit PROMs that support Master Serial, Slave Serial, Master SelectMAP, and Slave SelectMAP FPGA configuration modes (Figure 2). A summary of the Platform Flash PROM family members and supported features is shown in Table 1.
(c) 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
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Platform Flash In-System Programmable Configuration PROMs
R
CLK
CE
OE/RESET
TCK TMS TDI TDO
Control and JTAG Interface
Data
Memory
Address Data
Serial Interface
CEO DATA (D0) Serial Mode
CF
ds123_01_30603
Figure 1: XCFxxS Platform Flash Block Diagram
FI
CLK
CE
EN_EXT_SEL
OE/RESET
BUSY
CLKOUT TCK TMS TDI TDO
Control and JTAG Interface
OSC
Data Address
Memory
Data
Serial or Parallel Interface
CEO Data (D0) (Serial/Parallel Mode) D[1:7] (Parallel Mode)
Decompressor
CF
REV_SEL [1:0]
ds123_19_102003
Figure 2: XCFxxP Platform Flash Block Diagram When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after CE and OE are enabled, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin. New data is available a short access time after each rising clock edge. The FPGA generates the appropriate number of clock pulses to complete the configuration. When the FPGA is in Slave Serial mode, the PROM and the FPGA are both clocked by an external clock source, or optionally, for the XCFxxP PROM only, the PROM can be used to drive the FPGAs configuration clock. The XCFxxP version of the Platform Flash PROM also supports Master SelectMAP and Slave SelectMAP (or Slave Parallel) FPGA configuration modes. When the FPGA is in Master SelectMAP mode, the FPGA generates a configuration clock that drives the PROM. When the FPGA is in Slave SelectMAP Mode, either an external oscillator generates the configuration clock that drives the PROM and the FPGA, or optionally, the XCFxxP PROM can be used to drive the FPGAs configuration clock. After CE and OE are enabled, data is available on the PROMs DATA (D0-D7) pins. New data is available a short access time after each rising clock edge. The data is clocked into the FPGA on the following rising edge of the CCLK. A free-running oscillator can be used in the Slave Parallel /Slave SelecMAP mode. The XCFxxP version of the Platform Flash PROM provides additional advanced features. A built-in data decompressor supports utilizing compressed PROM files, and design revisioning allows multiple design revisions to be stored on a single PROM or stored across several PROMs. For design revisioning, external pins or internal Control bits are used to select the active design revision. Multiple Platform Flash PROM devices can be cascaded to support the larger configuration files required when targeting larger FPGA devices or targeting multiple FPGAs daisy chained together. When utilizing the advanced features for the XCFxxP Platform Flash PROM, such as design revisioning, programming files which span cascaded PROM devices can only be created for cascaded chains containing only XCFxxP PROMs. If the advanced XCFxxP features are not enabled, then the cascaded chain can include both XCFxxP and XCFxxS PROMs.
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Platform Flash In-System Programmable Configuration PROMs Table 2: Xilinx FPGAs and Compatible Platform Flash PROMs (Continued) FPGA Virtex
XCV50 XCV100 XCV150 XCV200 XCV300 1,305,440 3,006,560 4,485,472 8,214,624 11,589,984 15,868,256 19,021,408 26,099,040 34,292,832 43,602,784 360,096 635,296 1,697,184 2,761,888 4,082,592 5,659,296 7,492,000 10,494,368 15,659,936 21,849,504 29,063,072 630,048 863,840 1,442,016 1,875,648 2,693,440 3,430,400 3,961,632 6,519,648 6,587,520 8,308,992 10,159,648 12,922,336 16,283,712 XCF02S XCF04S XCF08P XCF08P XCF16P XCF16P XCF32P XCF32P XCF32P (2) XCF32P (2) XCF01S XCF01S XCF02S XCF04S XCF04S XCF08P XCF08P XCF16P XCF16P XCF32P XCF32P XCF01S XCF01S XCF02S XCF02S XCF04S XCF04S XCF04S XCF08P XCF08P XCF08P XCF16P XCF16P XCF16P XCV400 XCV600 XCV800 XCV1000 559,200 781,216 1,040,096 1,335,840 1,751,808 2,546,048 3,607,968 4,715,616 6,127,744 439,264 1,047,616 1,699,136 3,223,488 5,214,784 7,673,024 11,316,864 13,271,936 630,048 863,840 1,134,496 1,442,016 1,875,648 2,693,440 3,961,632 197,696 336,768 559,200 781,216 1,040,096 1,335,840 XCF01S XCF01S XCF01S XCF02S XCF02S XCF04S XCF04S XCF08P XCF08P XCF01S XCF01S XCF02S XCF04S XCF08P XCF08P XCF16P XCF16P XCF01S XCF01S XCF02S XCF02S XCF02S XCF04S XCF04S XCF01S XCF01S XCF01S XCF01S XCF01S XCF02S
The Platform Flash PROMs are compatible with all of the existing FPGA device families. A reference list of Xilinx FPGAs and the respective compatible Platform Flash PROMs is given in Table 2. A list of Platform Flash PROMs and their capacities is given in Table 3. Table 2: Xilinx FPGAs and Compatible Platform Flash PROMs FPGA Virtex-II Pro
XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VP100 XC2VP125
Configuration Bitstream
Platform Flash PROM (1)
Configuration Bitstream
Platform Flash PROM (1)
Spartan-3
XC3S50 XC3S200 XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000
Virtex-II
XC2V40 XC2V80 XC2V250 XC2V500 XC2V1000 XC2V1500 XC2V2000 XC2V3000 XC2V4000 XC2V6000 XC2V8000
Spartan-IIE
XC2S50E XC2S100E XC2S150E XC2S200E XC2S300E XC2S400E XC2S600E
Virtex-E
XCV50E XCV100E XCV200E XCV300E XCV400E XCV405E XCV600E XCV812E XCV1000E XCV1600E XCV2000E XCV2600E XCV3200E
Spartan-II
XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S200
Notes: 1. If design revisioning or other advanced feature support is required, the XCFxxP can be used as an alternative to the XCF01S, XCF02S, or XCF04S. 2. Assumes compression used.
Table 3: Platform Flash PROM Capacity
Platform Flash PROM Configuration Bits Platform Flash PROM Configuration Bits
XCF01S XCF02S XCF04S
1,048,576 2,097,152 4,194,304
XCF08P XCF16P XCF32P
8,388,608 16,777,216 33,554,432
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Platform Flash In-System Programmable Configuration PROMs
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Programming
In-System Programming
In-System Programmable PROMs can be programmed individually, or two or more can be daisy-chained together and programmed in-system via the standard 4-pin JTAG protocol as shown in Figure 3. In-system programming offers quick and efficient design iterations and eliminates unnecessary package handling or socketing of devices. The programming data sequence is delivered to the device using either Xilinx iMPACT software and a Xilinx download cable, a third-party JTAG development system, a JTAG-compatible board tester, or a simple microprocessor interface that emulates the JTAG instruction sequence. The iMPACT software also outputs serial vector format (SVF) files for use with any tools that accept SVF format, including automatic test equipment. During in-system programming, the CEO output is driven High. All other outputs are held in a high-impedance state or held at clamp levels during in-system programming. In-system programming is fully supported across the recommended operating voltage and temperature ranges. programmer. This provides the added flexibility of using pre-programmed devices with an in-system programmable option for future enhancements and design changes.
Reliability and Endurance
Xilinx in-system programmable products provide a guaranteed endurance level of 20,000 in-system program/erase cycles and a minimum data retention of 20 years. Each device meets all functional, performance, and data retention specifications within this endurance limit.
Design Security
The Xilinx in-system programmable Platform Flash PROM devices incorporate advanced data security features to fully protect the FPGA programming data against unauthorized reading via JTAG. The XCFxxP PROMs can also be programmed to prevent inadvertent writing via JTAG. Table 4 and Table 5 show the security settings available for the XCFxxS PROM and XCFxxP PROM, respectively.
Read Protection
The read protect security bit can be set by the user to prevent the internal programming pattern from being read or copied via JTAG. Read protection does not prevent write operations. For the XCFxxS PROM, the read protect security bit is set for the entire device, and resetting the read protect security bit requires erasing the entire device. For the XCFxxP PROM the read protect security bit can be set for individual design revisions, and resetting the read protect bit requires erasing the particular design revision.
GND
V CC
Write Protection
(a) (b)
DS026_02_082703
Figure 3: JTAG In-System Programming Operation
(a) Solder Device to PCB (b) Program Using Download Cable
OE/RESET
The 1/2/4 Mbit XCFxxS Platform Flash PROMs in-system programming algorithm requires issuance of a reset that causes OE/RESET to pulse Low.
The XCFxxP PROM device also allows the user to write protect (or lock) a particular design revision to prevent inadvertent erase or program operations. Once set, the write protect security bit for an individual design revision must be reset (using the UNLOCK command followed by ISC_ERASE command) before an erase or program operation can be performed. Table 4: XCFxxS Device Data Security Options Read Protect Reset (default) Set Read/Verify Inhibited Program Inhibited Erase Inhibited
External Programming
Xilinx reprogrammable PROMs can also be programmed by the Xilinx MultiPRO Desktop Tool or a third-party device
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Platform Flash In-System Programmable Configuration PROMs
Table 5: XCFxxP Design Revision Data Security Options Read Protect Reset (default) Reset (default) Set Set Write Protect Reset (default) Set Reset (default) Set Read/Verify Inhibited Program Inhibited Erase Inhibited
IEEE 1149.1 Boundary-Scan (JTAG)
The Platform Flash PROM family is IEEE Standard 1532 in-system programming compatible, and is fully compliant with the IEEE Std. 1149.1 Boundary-Scan, also known as JTAG, which is a subset of IEEE Std. 1532 Boundary-Scan. A Test Access Port (TAP) and registers are provided to support all required boundary scan instructions, as well as many of the optional instructions specified by IEEE Std. 1149.1. In addition, the JTAG interface is used to implement in-system programming (ISP) to facilitate configuration, erasure, and verification operations on the Platform Flash PROM device. Table 6 lists the required and optional boundary-scan instructions supported in the Platform Flash PROMs. Refer to the IEEE Std. 1149.1 specification for a complete description of boundary-scan architecture and the required and optional instructions. to a logic "0". The ISC Status field, IR[4], contains logic "1" if the device is currently in In-System Configuration (ISC) mode; otherwise, it contains logic "0". The Security field, IR[3], contains logic "1" if the device has been programmed with the security option turned on; otherwise, it contains logic "0". IR[2] is unused, and is set to '0'. The remaining bits IR[1:0] are set to '01' as defined by IEEE Std. 1149.1.
XCFxxP Instruction Register (16 bits wide)
The Instruction Register (IR) for the XCFxxP PROM is sixteen bits wide and is connected between TDI and TDO during an instruction scan sequence. The detailed composition of the instruction capture pattern is illustrated in Figure 5. The instruction capture pattern shifted out of the XCFxxP device includes IR[15:0]. IR[15:9] are reserved bits and are set to a logic "0". The ISC Error field, IR[8:7], contains a "10" when an ISC operation is a success, otherwise a "01" when an In-System Configuration (ISC) operation fails The Erase/Program (ER/PROG) Error field, IR[6:5], contains a "10" when an erase or program operation is a success, otherwise a "01" when an erase or program operation fails. The Erase/Program (ER/PROG) Status field, IR[4], contains a logic "1" when the device is busy performing an erase or programming operation, otherwise, it contains a logic "0". The ISC Status field, IR[3], contains logic "1" if the device is currently in In-System Configuration (ISC) mode; otherwise, it contains logic "0". The DONE field, IR[2], contains logic "1" if the sampled design revision has been successfully programmed; otherwise, a logic "0" indicates incomplete programming. The remaining bits IR[1:0] are set to '01' as defined by IEEE Std. 1149.1.
Instruction Register
The Instruction Register (IR) for the Platform Flash PROM is connected between TDI and TDO during an instruction scan sequence. In preparation for an instruction scan sequence, the instruction register is parallel loaded with a fixed instruction capture pattern. This pattern is shifted out onto TDO (LSB first), while an instruction is shifted into the instruction register from TDI.
XCFxxS Instruction Register (8 bits wide)
The Instruction Register (IR) for the XCFxxS PROM is eight bits wide and is connected between TDI and TDO during an instruction scan sequence. The detailed composition of the instruction capture pattern is illustrated in Figure 4. The instruction capture pattern shifted out of the XCFxxS device includes IR[7:0]. IR[7:5] are reserved bits and are set
Table 6: Platform Flash PROM Boundary Scan Instructions Boundary-Scan Command
Required Instructions BYPASS SAMPLE/PRELOAD EXTEST
XCFxxS IR[7:0] (hex)
XCFxxP IR[15:0] (hex)
Instruction Description
FF 01 00
FFFF 0001 0000
Enables BYPASS Enables boundary-scan SAMPLE/PRELOAD operation Enables boundary-scan EXTEST operation
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Platform Flash In-System Programmable Configuration PROMs Table 6: Platform Flash PROM Boundary Scan Instructions (Continued) Boundary-Scan Command
Optional Instructions CLAMP HIGHZ IDCODE USERCODE Platform Flash PROM Specific Instructions Initiates FPGA configuration by pulsing CF pin Low once. (For the XCFxxP this command also resets the selected design revision based on either the external REV_SEL[1:0] pins or on the internal design revision selection bits.) (1)
R
XCFxxS IR[7:0] (hex)
XCFxxP IR[15:0] (hex)
Instruction Description
FA FC FE FD
00FA 00FC 00FE 00FD
Enables boundary-scan CLAMP operation Places all outputs in high-impedance state simultaneously Enables shifting out 32-bit IDCODE Enables shifting out 32-bit USERCODE
CONFIG
EE
00EE
Notes: 1. For more information see Initiating FPGA Configuration.
TDI
IR[7:5] Reserved
IR[4] ISC Status
IR[3] Security
IR[2] 0
IR[1:0] 01
TDO
Figure 4: XCFxxS Instruction Capture Values Loaded into IR as part of an Instruction Scan Sequence IR[15:9] TDI Reserved IR[8:7] ISC Error IR[6:5] ER/PROG Error IR[4] ER/PROG Status IR[3] ISC Status IR[2] DONE IR[1:0] 01 TDO
Figure 5: XCFxxP Instruction Capture Values Loaded into IR as part of an Instruction Scan Sequence
Boundary Scan Register
The boundary-scan register is used to control and observe the state of the device pins during the EXTEST, SAMPLE/PRELOAD, and CLAMP instructions. Each output pin on the Platform Flash PROM has two register stages which contribute to the boundary-scan register, while each input pin has only one register stage. The bidirectional pins have a total of three register stages which contribute to the boundary-scan register. For each output pin, the register stage nearest to TDI controls and observes the output state, and the second stage closest to TDO controls and observes the High-Z enable state of the output pin. For each input pin, a single register stage controls and observes the input state of the pin. The bidirectional pin combines the three bits, the input stage bit is first, followed by the output stage bit and finally the output enable stage bit. The output enable stage bit is closest to TDO. See the XCFxxS/XCFxxP Pin Names and Descriptions Tables in the Pinouts and Pin Descriptions section for the boundary-scan bit order for all connected device pins, or see the appropriate BSDL file for the complete boundary-scan bit order description under the "attribute BOUNDARY_REGISTER" section in the BSDL file. The bit assigned to boundary-scan cell "0" is the LSB in the boundary-scan register, and is the register bit closest to TDO.
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Platform Flash In-System Programmable Configuration PROMs
Identification Registers
IDCODE Register
The IDCODE is a fixed, vendor-assigned value that is used to electrically identify the manufacturer and type of the device being addressed. The IDCODE register is 32 bits wide. The IDCODE register can be shifted out for examination by using the IDCODE instruction. The IDCODE is available to any other system component via JTAG. Table 7 lists the IDCODE register values for the Platform Flash PROMs. The IDCODE register has the following binary format: vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1 where v = the die version number f = the PROM family code a = the specific Platform Flash PROM product ID c = the Xilinx manufacture's ID The LSB of the IDCODE register is always read as logic "1" as defined by IEEE Std. 1149.1. Table 7: IDCODES Assigned to Platform Flash PROMs Device XCF01S XCF02S XCF04S XCF08P XCF16P XCF32P IDCODE (1) (hex) 05044093 05045093 05046093 05057093 05058093 05059093
USERCODE Register
The USERCODE instruction gives access to a 32-bit user programmable scratch pad typically used to supply information about the device's programmed contents. By using the USERCODE instruction, a user-programmable identification code can be shifted out for examination. This code is loaded into the USERCODE register during programming of the Platform Flash PROM. If the device is blank or was not loaded during programming, the USERCODE register contains FFFFFFFFh.
Customer Code Register
For the XCFxxP Platform Flash PROM, in addition to the USERCODE, a unique 32-byte Customer Code can be assigned to each design revision enabled for the PROM. The Customer Code is set during programming, and is typically used to supply information about the design revision contents. A private JTAG instruction is required to read the Customer Code. If the PROM is blank, or the Customer Code for the selected design revision was not loaded during programming, or if the particular design revision is erased, the Customer Code will contain all ones.
Platform Flash PROM TAP Characteristics
The Platform Flash PROM family performs both in-system programming and IEEE 1149.1 boundary-scan (JTAG) testing via a single 4-wire Test Access Port (TAP). This simplifies system designs and allows standard Automatic Test Equipment to perform both functions. The AC characteristics of the Platform Flash PROM TAP are described as follows.
Notes: 1. The first four bits indicate the die version number, and may vary.
TAP Timing
Figure 6 shows the timing relationships of the TAP signals. These TAP timing characteristics are identical for both boundary-scan and ISP operations.
TCKMIN
TCK
TMSS TMSH
TMS
TDIS TDIH
TDI
TDOV
TDO
DS026_04_020300
Figure 6: Test Access Port Timing
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Platform Flash In-System Programmable Configuration PROMs
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TAP AC Parameters
Table 8 shows the timing parameters for the TAP waveforms shown in Figure 6. Table 8: Test Access Port Timing Parameters Symbol TCKMIN1 TCKMIN2 TMSS TMSH TDIS TDIH TDOV Parameter TCK minimum clock period when VCCJ = 2.5V or 3.3V TCK minimum clock period, Bypass Mode, when VCCJ = 2.5V or 3.3V TMS setup time when VCCJ = 2.5V or 3.3V TMS hold time when VCCJ = 2.5V or 3.3V TDI setup time when VCCJ = 2.5V or 3.3V TDI hold time when VCCJ = 2.5V or 3.3V TDO valid delay when VCCJ = 2.5V or 3.3V Min 100 50 10 25 10 25 Max 30 Units ns ns ns ns ns ns ns
Additional Features for the XCFxxP
Internal Oscillator
The 8/16/32 Mbit XCFxxP Platform Flash PROMs include an optional internal oscillator which can be used to drive the CLKOUT and DATA pins on FPGA configuration interface. The internal oscillator can be enabled during device programming, and can be set to either the default frequency or to a slower frequency (AC Characteristics Over Operating Conditions When Cascading).
FPGA, clocking the FPGAs configuration logic. When the FPGA deasserts BUSY, indicating that it is ready to receive additional configuration data, the PROM will begin driving new data onto the configuration interface.
Decompression
The 8/16/32 Mbit XCFxxP Platform Flash PROMs include a built-in data decompressor compatible with Xilinx advanced compression technology. Compressed Platform Flash PROM files are created from the target FPGA bitstream(s) using the iMPACT software. Only Slave Serial and Slave SelectMAP (parallel) configuration modes are supported for FPGA configuration when using a XCFxxP PROM programmed with a compressed bitstream. Compression rates will vary depending on several factors, including the target device family and the target design contents. The decompression option is enabled during the PROM programming sequence. The PROM decompresses the stored data before driving both clock and data onto the FPGA's configuration interface. If Decompression is enabled, then the Platform Flash clock output pin (CLKOUT) must be used as the clock signal for the configuration interface, driving the target FPGA's configuration clock input pin (CCLK). Either the PROM's CLK input pin or the internal oscillator must be selected as the source for CLKOUT. Any target FPGA connected to the PROM must operate as slave in the configuration chain, with the configuration mode set to Slave Serial mode or Slave SelectMap (parallel) mode. When decompression is enabled, the CLKOUT signal becomes a controlled clock output with a reduced maximum frequency and remains Low when decompressed data is not ready. The BUSY input is automatically disabled when decompression is enabled.
CLKOUT
The 8/16/32 Mbit XCFxxP Platform Flash PROMs include the programmable option to enable the CLKOUT signal which allows the PROM to provide a source synchronous clock aligned to the data on the configuration interface. The CLKOUT signal is derived from one of two clock sources: the CLK input pin or the internal oscillator. The input clock source is selected during the PROM programming sequence. Output data is available on the rising edge of CLKOUT. The CLKOUT signal is enabled during programming, and is active when CE is Low and OE/RESET is High. When disabled, the CLKOUT pin is put into a high-impedance state and should be pulled High externally to provide a known state. When cascading Platform Flash PROMs with CLKOUT enabled, after completing it's data transfer, the first PROM disables CLKOUT and releases the CEO pin enabling the next PROM in the PROM chain. The next PROM will begin driving the CLKOUT signal once that PROM is enabled and data is available for transfer. During high-speed parallel configuration without compression, the FPGA drives the BUSY signal on the configuration interface. When BUSY is asserted High, the PROMs internal address counter stops incrementing, and the current data value is held on the data outputs. While BUSY is High, the PROM will continue driving the CLKOUT signal to the
Design Revisioning
Design Revisioning allows the user to create up to four unique design revisions on a single PROM or stored across
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Platform Flash In-System Programmable Configuration PROMs Revision 0 = '00' Revision 1 = '01' Revision 2 = '10' Revision 3 = '11' After programming the Platform Flash PROM, a particular design revision can be selected using the external REV_SEL[1:0] pins or using the internal programmable design revision control bits. The EN_EXT_SEL pin determines if the external pins or internal bits are used to select the design revision. When EN_EXT_SEL is Low, design revision selection is controlled by the external Revision Select pins, REV_SEL[1:0]. When EN_EXT_SEL is High, design revision selection is controlled by the internal programmable Revision Select control bits. During power up, the design revision selection inputs (pins or control bits) are sampled internally. After power up, the design revision selection inputs are sampled again after the rising edge of the CF pulse. The data from the selected design revision is then presented on the FPGA configuration interface.
multiple cascaded PROMs. Design Revisioning is supported for the 8/16/32 Mbit XCFxxP Platform Flash PROMs in both serial and parallel modes. Design Revisioning can be used with compressed PROM files, and also when the CLKOUT feature is enabled. The PROM programming files along with the revision information files (.cfi) are created using the iMPACT software. The .cfi file is required to enable design revision programming in iMPACT. A single design revision requires at least 8 Mbits of memory, but a larger design revision can span several devices. A single 32 Mbit PROM can store from one to four separate design revisions: one 32 Mbit design revision, two 16 Mbit design revisions, three 8 Mbit design revisions, or four 8 Mbit design revisions. A single 16 Mbit PROM can store up to two separate design revisions: one 16 Mbit design revision, two 8 Mbit design revisions. A single 8 Mbit PROM can store only one 8 Mbit design revision. Larger design revisions can be split over several cascaded PROMs. During the PROM file creation, each design revision is assigned a revision number:
PROM 0 REV 0 (8 Mbits) PROM 0 REV 0 (8 Mbits)
PROM 0
PROM 0 REV 0 (8 Mbits)
PROM 0
REV 0 (16 Mbits) REV 1 (8 Mbits) REV 1 (8 Mbits) REV 0 (32 Mbits) REV 2 (8 Mbits) REV 2 (16 Mbits) REV 3 (8 Mbits) REV 1 (16 Mbits) REV 1 (24 Mbits)
4 Design Revisions
3 Design Revisions
2 Design Revisions
1 Design Revision
(a) Design Revision storage examples for a single XCF32P PROM PROM 0 REV 0 (16 Mbits) PROM 0 REV 0 (16 Mbits) REV 0 (32 Mbits) REV 1 (16 Mbits) REV 1 (16 Mbits) REV 1 (16 Mbits) PROM 0 PROM 0 REV 0 (16 Mbits) REV 0 (32 Mbits) PROM 0
PROM 1 REV 2 (16 Mbits)
PROM 1
PROM 1
PROM 1
PROM 1
REV 2 (32 Mbits) REV 3 (16 Mbits)
REV 1 (32 Mbits)
REV 1 (32 Mbits)
REV 0 (32 Mbits)
4 Design Revisions
3 Design Revisions
2 Design Revisions
1 Design Revision
ds123_20_102103
(b) Design Revision storage examples spanning two XCF32P PROMs
Figure 7: Design Revision Storage Examples
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Platform Flash In-System Programmable Configuration PROMs
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PROM to FPGA Configuration Mode and Connections Summary
The FPGA's I/O, logical functions, and internal interconnections are established by the configuration data contained in the FPGAs bitstream. The bitstream is loaded into the FPGA either automatically upon power up, or on command, depending on the state of the FPGA's mode pins. Xilinx Platform Flash PROMs are designed to download directly to the FPGA configuration interface. FPGA configuration modes which are supported by the XCFxxS Platform Flash PROMs include: Master Serial and Slave Serial. FPGA configuration modes which are supported by the XCFxxP Platform Flash PROMs include: Master Serial, Slave Serial, Master SelectMAP, and Slave SelectMAP. Below is a short summary of the supported FPGA configuration modes. See the respective FPGA data sheet for device configuration details, including which configuration modes are supported by the targeted FPGA device. The CE input of the first (or only) PROM can be driven by the DONE output of all target FPGA devices, provided that DONE is not permanently grounded. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary ICC active supply current (DC Characteristics Over Operating Conditions). The PROM CF pin is typically connected to the FPGA's PROG_B (or PROGRAM) input.
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FPGA Slave Serial Mode
In Slave Serial mode, the FPGA loads the configuration bitstream in bit-serial form from external memory synchronized by an externally supplied clock. Upon power-up or reconfiguration, the FPGA's mode select pins are used to select the Slave Serial configuration mode. Slave Serial Mode provides a simple configuration interface. Only a serial data line, a clock line, and two control lines (INIT and DONE) are required to configure an FPGA. Data from the PROM is read out sequentially on a single data line (DIN), accessed via the PROM's internal address counter which is incremented on every valid rising edge of CCLK. The serial bitstream data must be setup at the FPGAs DIN input pin a short time before each rising edge of the externally provided CCLK. Connecting the FPGA device to the configuration PROM for Slave Serial Configuration Mode (Figure 9): * * * * The DATA output of the PROM(s) drive the DIN input of the lead FPGA device. The PROM CLKOUT (for XCFxxP only) or an external clock source drives the FPGA's CCLK input. The CEO output of a PROM drives the CE input of the next PROM in a daisy chain (if any). The OE/RESET pins of all PROMs are connected to the INIT_B (or INIT) pins of all FPGA devices. This connection assures that the PROM address counter is reset before the start of any (re)configuration. The PROM CE input can be driven from the DONE pin. The CE input of the first (or only) PROM can be driven by the DONE output of all target FPGA devices, provided that DONE is not permanently grounded. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary ICC active supply current (DC Characteristics Over Operating Conditions). The PROM CF pin is typically connected to the FPGA's PROG_B (or PROGRAM) input.
FPGA Master Serial Mode
In Master Serial mode, the FPGA automatically loads the configuration bitstream in bit-serial form from external memory synchronized by the configuration clock (CCLK) generated by the FPGA. Upon power-up or reconfiguration, the FPGA's mode select pins are used to select the Master Serial configuration mode. Master Serial Mode provides a simple configuration interface. Only a serial data line, a clock line, and two control lines (INIT and DONE) are required to configure an FPGA. Data from the PROM is read out sequentially on a single data line (DIN), accessed via the PROM's internal address counter which is incremented on every valid rising edge of CCLK. The serial bitstream data must be setup at the FPGAs DIN input pin a short time before each rising edge of the FPGA's internally generated CCLK signal. Typically, a wide range of frequencies can be selected for the FPGA's internally generated CCLK which always starts at a slow default frequency. The FPGAs bitstream contains configuration bits which can switch CCLK to a higher frequency for the remainder of the Master Serial configuration sequence. The desired CCLK frequency is selected during bitstream generation. Connecting the FPGA device to the configuration PROM for Master Serial Configuration Mode (Figure 8): * * * * The DATA output of the PROM(s) drive the DIN input of the lead FPGA device. The Master FPGA CCLK output drives the CLK input(s) of the PROM(s) The CEO output of a PROM drives the CE input of the next PROM in a daisy chain (if any). The OE/RESET pins of all PROMs are connected to the INIT_B pins of all FPGA devices. This connection assures that the PROM address counter is reset before the start of any (re)configuration. The PROM CE input can be driven from the DONE pin.
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Serial Daisy Chain
Multiple FPGAs can be daisy-chained for serial configuration from a single source. After a particular FPGA has been configured, the data for the next device is routed internally
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Platform Flash In-System Programmable Configuration PROMs * * The CEO output of a PROM drives the CE input of the next PROM in a daisy chain (if any). The OE/RESET pins of all PROMs are connected to the INIT_B pins of all FPGA devices. This connection assures that the PROM address counter is reset before the start of any (re)configuration. The PROM CE input can be driven from the DONE pin. The CE input of the first (or only) PROM can be driven by the DONE output of all target FPGA devices, provided that DONE is not permanently grounded. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary ICC active supply current (DC Characteristics Over Operating Conditions). For high-frequency parallel configuration, the BUSY pins of all PROMs are connected to the FPGA's BUSY output. This connection assures that the PROM is only enabled when the FPGA is ready for the next configuration data byte. The PROM CF pin is typically connected to the FPGA's PROG_B (or PROGRAM) input.
to the FPGAs DOUT pin. Typically the data on the DOUT pin changes on the falling edge of CCLK, although for some devices the DOUT pin changes on the rising edge of CCLK. Consult the respective device data sheets for detailed information on a particular FPGA device. For clocking the daisy-chained configuration, either the first FPGA in the chain can be set to Master Serial, generating the CCLK, with the remaining devices set to Slave Serial (Figure 10), or all the FPGA devices can be set to Slave Serial and an externally generated clock can be used to drive the FPGA's configuration interface.
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FPGA Master SelectMAP (Parallel) Mode(1)
In Master SelectMAP mode, byte-wide data is written into the FPGA, typically with a BUSY flag controlling the flow of data, synchronized by the configuration clock (CCLK) generated by the FPGA. Upon power-up or reconfiguration, the FPGA's mode select pins are used to select the Master SelectMAP configuration mode. The configuration interface typically requires a parallel data bus, a clock line, and two control lines (INIT and DONE). In addition, the FPGAs Chip Select, Write, and BUSY pins must be correctly controlled to enable SelectMAP configuration. The configuration data is read from the PROM byte by byte on pins [D0..D7], accessed via the PROM's internal address counter which is incremented on every valid rising edge of CCLK. The bitstream data must be setup at the FPGAs [D0..D7] input pins a short time before each rising edge of the FPGA's internally generated CCLK signal. If BUSY is asserted (High) by the FPGA, the configuration data must be held until BUSY goes Low. An external data source or external pull-down resistors must be used to enable the FPGA's active Low Chip Select (CS or CS_B) and Write (WRITE or RDWR_B) signals to enable the FPGA's SelectMAP configuration process. The Master SelectMAP configuration interface is clocked by the FPGA's internal oscillator. Typically, a wide range of frequencies can be selected for the internally generated CCLK which always starts at a slow default frequency. The FPGAs bitstream contains configuration bits which can switch CCLK to a higher frequency for the remainder of the Master SelectMAP configuration sequence. The desired CCLK frequency is selected during bitstream generation. Connecting the FPGA device to the configuration PROM for Master SelectMAP (Parallel) Configuration Mode (Figure 11): * * The DATA outputs of the PROM(s) drive the [D0..D7] input of the lead FPGA device. The Master FPGA CCLK output drives the CLK input(s) of the PROM(s) *
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FPGA Slave SelectMAP (Parallel) Mode(2)
In Slave SelectMAP mode, byte-wide data is written into the FPGA, typically with a BUSY flag controlling the flow of data, synchronized by an externally supplied configuration clock (CCLK). Upon power-up or reconfiguration, the FPGA's mode select pins are used to select the Slave SelectMAP configuration mode. The configuration interface typically requires a parallel data bus, a clock line, and two control lines (INIT and DONE). In addition, the FPGAs Chip Select, Write, and BUSY pins must be correctly controlled to enable SelectMAP configuration. The configuration data is read from the PROM byte by byte on pins [D0..D7], accessed via the PROM's internal address counter which is incremented on every valid rising edge of CCLK. The bitstream data must be setup at the FPGAs [D0..D7] input pins a short time before each rising edge of the provided CCLK. If BUSY is asserted (High) by the FPGA, the configuration data must be held until BUSY goes Low. An external data source or external pull-down resistors must be used to enable the FPGA's active Low Chip Select (CS or CS_B) and Write (WRITE or RDWR_B) signals to enable the FPGA's SelectMAP configuration process. After configuration, the pins of the SelectMAP port can be used as additional user I/O. Alternatively, the port can be retained using the persist option. Connecting the FPGA device to the configuration PROM for Slave SelectMAP (Parallel) Configuration Mode (Figure 12):
1. The Master SelectMAP (Parallel) FPGA configuration mode is supported only by the XCFxxP Platform Flash PROM. This mode is not supported by the XCFxxS Platform Flash PROM.
2. The Slave SelectMAP (Parallel) FPGA configuration mode is supported only by the XCFxxP Platform Flash PROMs.This mode is not supported by the XCFxxS Platform Flash PROM.
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Platform Flash In-System Programmable Configuration PROMs * * * * The DATA outputs of the PROM(s) drives the [D0..D7] inputs of the lead FPGA device. The PROM CLKOUT (for XCFxxP only) or an external clock source drives the FPGA's CCLK input The CEO output of a PROM drives the CE input of the next PROM in a daisy chain (if any). The OE/RESET pins of all PROMs are connected to the INIT_B pins of all FPGA devices. This connection assures that the PROM address counter is reset before the start of any (re)configuration. The PROM CE input can be driven from the DONE pin. The CE input of the first (or only) PROM can be driven by the DONE output of all target FPGA devices, provided that DONE is not permanently grounded. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary ICC active supply current (DC Characteristics Over Operating Conditions). For high-frequency parallel configuration, the BUSY pins of all PROMs are connected to the FPGA's BUSY output. This connection assures that the PROM is only enabled when the FPGA is ready for the next configuration data byte. The PROM CF pin is typically connected to the FPGA's PROG_B (or PROGRAM) input.
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For clocking the parallel configuration chain, either the first FPGA in the chain can be set to Master SelectMAP, generating the CCLK, with the remaining devices set to Slave SelectMAP, or all the FPGA devices can be set to Slave SelectMAP and an externally generated clock can be used to drive the configuration interface. Again, the respective device data sheets should be consulted for detailed information on a particular FPGA device, including which configuration modes are supported by the targeted FPGA device.
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Cascading Configuration PROMs
When configuring multiple FPGAs in a serial daisy chain, configuring multiple FPGAs in a SelectMAP parallel chain, or configuring a single FPGA requiring a larger configuration bitstream, cascaded PROMs provide additional memory (Figure 10, Figure 13, Figure 14, and Figure 15). Multiple Platform Flash PROMs can be concatenated by using the CEO output to drive the CE input of the downstream device. The clock signal and the data outputs of all Platform Flash PROMs in the chain are interconnected. After the last data from the first PROM is read, the first PROM asserts its CEO output Low and drives its outputs to a high-impedance state. The second PROM recognizes the Low level on its CE input and immediately enables its outputs. After configuration is complete, address counters of all cascaded PROMs are reset if the PROM OE/RESET pin goes Low or CE goes High. When utilizing the advanced features for the XCFxxP Platform Flash PROM, including the clock output (CLKOUT) option, decompression option, or design revisioning, programming files which span cascaded PROM devices can only be created for cascaded chains containing only XCFxxP PROMs. If the advanced features are not used, then cascaded PROM chains can contain both XCFxxP and XCFxxS PROMs.
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FPGA SelectMAP (Parallel) Device Chaining(1)
Multiple Virtex-II FPGAs can be configured using the SelectMAP mode, and be made to start-up simultaneously. To configure multiple devices in this way, wire the individual CCLK, DONE, INIT, Data ([D0..D7]), Write (WRITE or RDWR_B), and BUSY pins of all the devices in parallel. If all devices are to be configured with the same bitstream, readback is not being used, and the CCLK frequency selected does not require the use of the BUSY signal, the CS_B pins can be connected to a common line so all of the devices are configured simultaneously (Figure 13). With additional control logic, the individual devices can be loaded separately by asserting the CS_B pin of each device in turn and then enabling the appropriate configuration data. The PROM can also store the individual bitstreams for each FPGA for SelectMAP configuration in separate design revisions. When design revisioning is utilized, additional control logic can be used to select the appropriate bitstream by asserting the EN_EXT_SEL pin, and using the REV_SEL[1:0] pins to select the required bitstream, while asserting the CS_B pin for the FPGA the bitstream is targeting (Figure 14).
Initiating FPGA Configuration
The options for initiating FPGA configuration via the Platform Flash PROM include: 1. Automatic configuration on power up 2. Applying an external PROG_B (or PROGRAM) pulse 3. Applying the JTAG CONFIG instruction Following the FPGA's power-on sequence or the assertion of the PROG_B (or PROGRAM) pin the FPGAs configuration memory is cleared, the configuration mode is selected, and the FPGA is ready to accept a new configuration bitstream. The FPGA's PROG_B pin can be controlled by an external source, or alternatively, the Platform Flash PROMs incorporate a CF pin that can be tied to the FPGAs PROG_B pin. Executing the CONFIG instruction through JTAG pulses the CF output Low once for 300-500 ns, resetting the FPGA and initiating configuration. The iMPACT soft-
1. The SelectMAP (Parallel) FPGA configuration modes are supported only by the XCFxxP Platform Flash PROM.These modes are not supported by the XCFxxS Platform Flash PROM.
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Platform Flash In-System Programmable Configuration PROMs the FPGA is reset. The XCFxxP PROM samples the current design revision selection from the external REV_SEL pins or the internal programmable Revision Select bits on the rising edge of CF. When the JTAG CONFIG command is executed, the XCFxxP will sample the new design revision before initiating the FPGA configuration sequence.
ware can issue the JTAG CONFIG command to initiate FPGA configuration by setting the "Load FPGA" option. When using the XCFxxP Platform Flash PROM with design revisioning enabled, the CF pin should always be connected to the PROG_B (or PROGRAM) pin on the FPGA to ensure that the current design revision selection is sampled when
Configuration PROM to FPGA Device Interface Connection Diagrams
VCCO
(2)
4.7 k
4.7 k
(1)
VCCJ VCCO VCCINT
VCCINT VCCO
(2)
D0
DIN
MODE PINS
(1)
VCCJ(2)
DIN CCLK
Platform Flash PROM
CLK CE CEO OE/RESET TDI TMS TCK TDO TDO GND TDI TDI TMS TCK CF
Xilinx FPGA Master Serial
CCLK DONE DOUT INIT_B PROG_B
DONE INIT_B PROG_B
...OPTIONAL Slave FPGAs with identical configurations
DOUT CCLK DONE INIT_B PROG_B
...OPTIONAL Daisy-chained Slave FPGAs with different configurations
TMS TCK TDO
GND
Notes: 1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet. 2 For compatible voltages, refer to the appropriate data sheet.
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Figure 8: Configuring in Master Serial Mode
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Platform Flash In-System Programmable Configuration PROMs
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VCCO External (3) Oscillator 4.7 k
(2)
4.7 k
(1)
VCCJ VCCO VCCINT
VCCINT VCCO VCCJ
(2) (2)
D0
DIN
MODE PINS
(1)
DIN CCLK
Platform Flash PROM
CLK
(3)
Xilinx FPGA Slave Serial
CCLK DONE DOUT INIT_B PROG_B
DONE INIT_B PROG_B
...OPTIONAL Slave FPGAs with identical configurations
CE CEO OE/RESET TDI TMS TCK TDO TDO GND TDI TMS TCK CF
DOUT CCLK DONE INIT_B PROG_B
...OPTIONAL Daisy-chained Slave FPGAs with different configurations
TDI TMS TCK TDO
GND
Notes: 1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet. 2 For compatible voltages, refer to the appropriate data sheet. 3 In Slave Serial mode, the configuration interface can be clocked by an external oscillator, or optionally--for the XCFxxP Platform Flash PROM only--the CLKOUT signal can be used to drive the FPGA's configuration clock (CCLK). If the XCFxxP PROM's CLKOUT signal is used, then it must be tied to a 4.7K resistor pulled up to VCCO.
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Figure 9: Configuring in Slave Serial Mode
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Platform Flash In-System Programmable Configuration PROMs
VCCJ VCCO VCCINT
VCCJ VCCO VCCINT
VCCO
(2)
4.7 k
4.7 k
(1)
VCCINT VCCO VCCJ
(2) (2)
D0
VCCINT VCCO VCCJ
(2) (2)
D0
DIN
MODE PINS
(1)
MODE PINS DIN
(1)
DOUT
Platform Flash PROM Cascaded PROM (PROM 1)
TDI TMS TCK TDO CLK CE CEO OE/RESET TDI TMS TCK TDO CF
Platform Flash PROM First PROM (PROM 0)
CLK CE CEO OE/RESET CF TDI TMS TCK TDO TDI
Xilinx FPGA Master Serial
CCLK DONE INIT_B PROG_B
Xilinx FPGA Slave Serial
CCLK DONE INIT_B PROG_B
TDO
TDI TMS TCK TDO
GND
GND
TMS TCK
GND
GND
Notes: 1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet. 2 For compatible voltages, refer to the appropriate data sheet.
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Figure 10: Configuring Multiple Devices Master/Slave Serial Mode
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Platform Flash In-System Programmable Configuration PROMs
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VCCO
(2)
4.7 k
4.7 k
(1)
VCCJ VCCO VCCINT
VCCINT VCCO(2) VCCJ
(2)
D[0:7]
D[0:7]
MODE PINS
(1)
I/O(3) I/O 1K 1K
(3)
RDWR_B CS_B
XCFxxP Platform Flash PROM
CLK CE CEO OE/RESET TDI TMS TCK TDO TDO GND TDI TMS TCK CF BUSY
(4)
Xilinx FPGA Master SelectMAP
CCLK DONE
D[0:7] INIT_B PROG_B BUSY(4) CCLK DONE INIT_B PROG_B BUSY TDI TMS TCK TDO
(4)
...OPTIONAL Slave FPGAs with identical configurations
GND
Notes: 1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet. 2 For compatible voltages, refer to the appropriate data sheet. 3 CS_B (or CS) and RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown. 4 The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only required for high-frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet.
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Figure 11: Configuring in Master SelectMAP Mode
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Platform Flash In-System Programmable Configuration PROMs
VCCO External (5) Oscillator 4.7 k
(2)
4.7 k
(1)
VCCJ VCCO VCCINT
VCCINT VCCO(2) VCCJ(2)
D[0:7]
D[0:7]
MODE PINS
(1)
I/O
(3)
RDWR_B CS_B 1K 1K
I/O(3)
XCFxxP Platform Flash PROM
CLK
(5)
Xilinx FPGA Slave SelectMAP
CCLK DONE
CE CEO OE/RESET TDI TMS TCK TDO TDO GND TDI TMS TCK CF BUSY
(4)
D[0:7] INIT_B PROG_B BUSY(4) CCLK DONE INIT_B PROG_B BUSY TDI TMS TCK TDO
(4)
...OPTIONAL Slave FPGAs with identical configurations
GND
Notes: 1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet. 2 For compatible voltages, refer to the appropriate data sheet. 3 CS_B (or CS) and RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown. 4 The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only required for high-frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet. 5 If the XCFxxP Platform Flash PROM is not used with CLKOUT enabled to drive CCLK, then an external clock is required for Slave SelectMAP (or Slave Parallel) modes. If CLKOUT is used, then it must be tied to a 4.7K resistor pulled up to VCCO.
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Figure 12: Configuring in Slave SelectMAP Mode
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Platform Flash In-System Programmable Configuration PROMs
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VCCJ VCCO VCCINT
VCCJ VCCO VCCINT
VCCO(2)
4.7 k
4.7 k
(1)
VCCINT VCCO VCCJ
(2) (2)
D[0:7]
VCCINT VCCO
(2)
D[0:7]
D[0:7]
MODE PINS
(1)
D[0:7] I/O
(3)
MODE PINS
(1)
I/O RDWR_B CS_B 1K 1K
(3)
VCCJ(2)
RDWR_B CS_B 1K
I/O(3) 1K
I/O(3)
XCFxxP Platform Flash PROM Cascaded PROM (PROM 1)
TDI TMS TCK TDO GND TDI TMS TCK CLK CE CEO CF BUSY
(4)
XCFxxP Platform Flash PROM First PROM (PROM 0)
CLK CE CEO
Xilinx FPGA Master SelectMAP
CCLK DONE INIT_B PROG_B BUSY
(4)
Xilinx FPGA Slave SelectMAP
CCLK DONE INIT_B PROG_B BUSY
(4)
OE/RESET
OE/RESET CF BUSY TDI TMS TCK GND TDO
(4)
TDO
TDO TDI TMS TCK TDI TMS TCK TDO
GND
GND
Notes: 1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet. 2 For compatible voltages, refer to the appropriate data sheet. 3 CS_B (or CS) and RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown. 4 The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only required for high-frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet.
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Figure 13: Configuring Multiple Devices with Identical Patterns in Master/Slave SelectMAP Mode
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Platform Flash In-System Programmable Configuration PROMs
VCCJ VCCO VCCINT
VCCJ VCCO VCCINT
VCCO(2)
External (3) Oscillator
(1)
4.7 k
4.7 k
VCCINT VCCO
(2)
D0
VCCINT VCCO VCCJ
(2) (2)
D0
DIN
MODE PINS
(1)
MODE PINS DIN
(1)
DOUT
VCCJ(2)
XCFxxP Platform Flash PROM Cascaded PROM (PROM 1)
TDI TMS TCK TDO TDI TMS TCK TDO CLK
(3)
XCFxxP Platform Flash PROM First PROM (PROM 0)
CLK
(3)
Xilinx FPGA Slave Serial
CCLK DONE INIT_B PROG_B
Xilinx FPGA Slave Serial
CCLK DONE INIT_B PROG_B
CE CEO CF
CE CEO CF
OE/RESET
OE/RESET
TDI TMS TCK TDO TDI TMS TCK TDI TMS TCK TDO
EN_EX_SEL REV_SEL[1:0] GND
EN_EX_SEL REV_SEL[1:0] GND
GND
GND
EN_EXT_SEL Design Revision Control Logic REV_SEL[1:0] DONE CF / PROG_B Notes: 1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet. 2 For compatible voltages, refer to the appropriate data sheet. 3 In Slave Serial mode, the configuration interface can be clocked by an external oscillator, or optionally the CLKOUT signal can be used to drive the FPGA's configuration clock (CCLK). If the XCFxxP PROM's CLKOUT signal is used, then it must be tied to a 4.7K resistor pulled up to VCCO.
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Figure 14: Configuring Multiple Devices with Design Revisioning in Slave Serial Mode
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Platform Flash In-System Programmable Configuration PROMs
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VCCJ
VCCO VCCINT
VCCJ
VCCO VCCINT
VCCO
(2)
External (5) Oscillator
4.7 k 4.7 k
(1)
VCCINT VCCO VCCJ
(2) (2)
D[0:7]
VCCINT VCCO
(2)
D[0:7]
D[0:7]
MODE PINS
(1)
D[0:7] I/O(3) 1K
MODE PINS
(1)
RDWR_B CS_B
RDWR_B CS_B I/O 1K
(3)
VCCJ(2)
XCFxxP Platform Flash PROM Cascaded PROM (PROM 1)
TDI TMS TCK TDO TDI TMS TCK CLK
(5)
XCFxxP Platform Flash PROM First PROM (PROM 0)
CLK
(5)
Xilinx FPGA Slave SelectMAP
CCLK DONE INIT_B PROG_B BUSY
(4)
Xilinx FPGA Slave SelectMAP
CCLK DONE INIT_B PROG_B BUSY
(4)
CE CEO CF
CE CEO CF BUSY
(4)
OE/RESET BUSY
(4)
OE/RESET
TDO
TDI TMS TCK TDO TDI TMS TCK TDO TDI TMS TCK TDO
EN_EX_SEL REV_SEL[1:0] GND
EN_EX_SEL REV_SEL[1:0] GND
GND
GND
EN_EXT_SEL Design Revision Control Logic REV_SEL[1:0] CF DONE PROG_B CS_B[1:0]
Notes: 1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet. 2 For compatible voltages, refer to the appropriate data sheet. 3 RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown. 4 The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only required for high frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet. 5 In Slave SelectMAP mode, the configuration interface can be clocked by an external oscillator, or optionally the CLKOUT signal can be used to drive the FPGA's configuration clock (CCLK). If the XCFxxP PROM's CLKOUT signal is used, then it must be tied to a 4.7K resistor pulled up to VCCO.
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Figure 15: Configuring Multiple Devices with Design Revisioning in Slave SelectMAP Mode
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DS123 (v2.1) November 18, 2003 Preliminary Product Specification
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Platform Flash In-System Programmable Configuration PROMs
Reset and Power-On Reset Activation
At power up, the device requires the VCCINT power supply to monotonically rise to the nominal operating voltage within the specified VCCINT rise time. If the power supply cannot meet this requirement, then the device might not perform power-on reset properly. During the power-up sequence, OE/RESET is held Low by the PROM. Once the required supplies have reached their respective POR (Power On Reset) thresholds, the OE/RESET release is delayed (TOER minimum) to allow more margin for the power supplies to stabilize before initiating configuration. The OE/RESET pin is connected to an external pull-up resistor and also to the target FPGA's INIT pin. For systems utilizing slow-rising power supplies, an additional power monitoring circuit can be used to delay the target configuration until the system power reaches minimum operating voltages by holding the OE/RESET pin Low. When OE/RESET is released, the FPGAs INIT pin is pulled High allowing the FPGA's configuration sequence to begin. If the power drops below the power-down threshold (VCCPD), the PROM resets and OE/RESET is again held Low until the after the POR threshold is reached. OE/RESET polarity is not programmable. These power-up requirements are shown graphically in Figure 16. For a fully powered Platform Flash PROM, a reset occurs whenever OE/RESET is asserted (Low) or CE is deasserted (High). The address counter is reset, CEO is driven High, and the remaining outputs are placed in a high-impedance state. Notes: 1. The XCFxxS PROM only requires VCCINT to rise above its POR threshold before releasing OE/RESET. 2. The XCFxxP PROM requires both VCCINT to rise above its POR threshold and for VCCO to reach the recommended operating voltage level before releasing OE/RESET.
VCCINT
Recommended Operating Range Delay or Restart Configuration
200 s ramp
50 ms ramp
VCCPOR VCCPD
A slow-ramping VCCINT supply may still be below the minimum operating voltage when OE/RESET is released. In this case, the configuration sequence must be delayed until both VCCINT and VCCO have reached their recommended operating conditions.
TIME (ms) TRST
ds123_21_103103
TOER
TOER
Figure 16: Platform Flash PROM Power-Up Requirements
I/O Input Voltage Tolerance and Power Sequencing
The I/Os on each re-programmable Platform Flash PROM are fully 3.3V-tolerant. This allows 3V CMOS signals to connect directly to the inputs without damage. The VCCINT power can be applied before or after 3V CMOS signals are applied to the I/Os. The core power supply (VCCINT), JTAG pin power supply (VCCJ), and output power supply (VCCO) can be applied in any order. The PROM should not be partially powered, with one supply left unpowered while another supply is fully powered. Failure to power the PROM correctly may result in damage to the device. Additionally, for the XCFxxS PROM only, when VCCO is supplied at 2.5V or 3.3V and VCCINT is supplied at 3.3V, the I/Os
are 5V-tolerant. This allows 5V CMOS signals to connect directly to the inputs on a powered XCFxxS PROM without damage.
Standby Mode
The PROM enters a low-power standby mode whenever CE is deasserted (High). In standby mode, the address counter is reset, CEO is driven High, and the remaining outputs are placed in a high-impedance state regardless of the state of the OE/RESET input. For the device to remain in the low-power standby mode, the JTAG pins TMS, TDI, and TDO must not be pulled Low, and TCK must be stopped (High or Low).
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Table 9: Truth Table for XCFxxS PROM Control Inputs Control Inputs OE/RESET
High Low X (1)
Outputs Internal Address
If address < TC (2) : increment TC (2)
CE
Low If address = Low High Held reset Held reset
DATA
Active High-Z High-Z High-Z
CEO
High Low High High
ICC
Active Reduced Active Standby
: don't change
Notes: 1. X = don't care. 2. TC = Terminal Count = highest address value. TC + 1 = address 0.
Table 10: Truth Table for XCFxxP PROM Control Inputs Control Inputs OE/RESET CE BUSY Internal Address
If address < TC (2) and address < EA (3) : increment High Low Low If address < TC (2) and address = EA (3) : don't change Else if address = TC (2) : don't change High Low X (1) Low Low High High X X Unchanged Held reset (4) Held reset (4)
Outputs DATA
Active High-Z High-Z Active and Unchanged High-Z High-Z
CEO
High High Low High High High
CLKOUT
Active High-Z High-Z Active High-Z High-Z
ICC
Active Reduced Reduced Active Active Standby
Notes: 1. X = don't care. 2. TC = Terminal Count = highest address value. 3. For the XCFxxP with Design Revisioning enabled, EA = end address (last address in the selected design revision). 4. For the XCFxxP with Design Revisioning enabled, Held Reset = address reset to the beginning address of the selected bank. If Design Revisioning is not enabled, then Held Reset = address reset to address 0.
DC Electrical Characteristics
*Absolute Maximum Ratings, page 23 *Supply Voltage Requirements for Power-On Reset and Power-Down, page 23 *Recommended Operating Conditions, page 24 *Quality and Reliability Characteristics, page 24 *DC Characteristics Over Operating Conditions, page 25
AC Electrical Characteristics
*AC Characteristics Over Operating Conditions, page 26 *AC Characteristics Over Operating Conditions When Cascading, page 29
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Platform Flash In-System Programmable Configuration PROMs
Absolute Maximum Ratings
Symbol
VCCINT VCCO VCCJ VIN
Description
Internal supply voltage relative to GND I/O supply voltage relative to GND JTAG I/O supply voltage relative to GND Input voltage with respect to GND VCCO < 2.5V VCCO 2.5V VCCO < 2.5V VCCO 2.5V
XCF01S, XCF02S, XCF04S
-0.5 to +4.0 -0.5 to +4.0 -0.5 to +4.0 -0.5 to +3.6 -0.5 to +5.5 -0.5 to +3.6 -0.5 to +5.5 -65 to +150 +220 +125
XCF08P, XCF16P, XCF32P
-0.5 to +2.7 -0.5 to +4.0 -0.5 to +4.0 -0.5 to VCCO + 0.5 -0.5 to VCCO + 0.5 -0.5 to VCCO + 0.5 -0.5 to VCCO + 0.5 -65 to +150 +220 +125
Units
V V V V V V V C C C
VTS TSTG TSOL(3) TJ
Voltage applied to High-Z output Storage temperature (ambient)
Maximum soldering temperature (10s @ 1/16 in.) Junction temperature
Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins can undershoot to -2.0V or overshoot to +7.0V, provided this over- or undershoot lasts less then 10 ns and with the forcing current being limited to 200 mA. 2. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time adversely affects device reliability. 3. For soldering guidelines, see the information on "Packaging and Thermal Characteristics" at www.xilinx.com.
Supply Voltage Requirements for Power-On Reset and Power-Down
XCF01S, XCF02S, XCF04S Symbol
VCCPOR TOER TVCC TRST VCCPD
XCF08P, XCF16P, XCF32P Min
TBD 0 0.2 10 -
Description
POR threshold for the VCCINT supply OE/RESET release delay following POR (4)
Min
1 0 0.2 10 -
Max
1 50 1
Max
TBD 50 TBD
Units
V ms ms ms V
VCCINT rise time from 0V to nominal voltage Time required to trigger a device reset when the VCCINT supply drops below the maximum VCCPD threshold Power-down threshold for VCCINT supply
Notes: 1. VCCINT, VCCO, and VCCJ supplies may be applied in any order. 2. At power up, the device requires the VCCINT power supply to monotonically rise to the nominal operating voltage within the specified TVCC rise time. If the power supply cannot meet this requirement, then the device might not perform power-on-reset properly. See Figure 16, page 21. 3. If the VCCINT and VCCO supplies do not reach their respective recommended operating conditions before the OE/RESET pin is released, then the configuration data from the PROM will not be available at the recommended threshold levels. The configuration sequence must be delayed until both VCCINT and VCCO have reached their recommended operating conditions.
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Platform Flash In-System Programmable Configuration PROMs
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Recommended Operating Conditions
XCF01S, XCF02S, XCF04S Symbol
VCCINT
XCF08P, XCF16P, XCF32P Min
1.65 3.0 2.3 1.7 TBD 0 0 2.0 70% VCCO 0 -40
Description
Internal voltage supply 3.3V Operation
Min
3.0 3.0 2.3 1.7 0 0 2.0 70% VCCO 0 -40
Max
3.6 3.6 2.7 2.0 0.8 20% VCCO 5.5 3.6 VCCO 85
Max
2.0 3.6 2.7 2.0 TBD 0.8 20% VCCO 3.6 3.6 VCCO 85
Units
V V V V V V V V V V C
VCCO/VCCJ
Supply voltage for output drivers
2.5V Operation 1.8V Operation 1.5V Operation 2.5V or 3.3V Operation
VIL
Low-level input voltage 1.8V Operation 2.5V or 3.3V Operation High-level input voltage 1.8V Operation Output voltage Operating ambient temperature
VIH VO TA
Quality and Reliability Characteristics
Symbol
TDR NPE VESD Data retention Program/erase cycles (Endurance) Electrostatic discharge (ESD)
Description
Min
20 20,000 2,000
Max
-
Units
Years Cycles Volts
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Platform Flash In-System Programmable Configuration PROMs
DC Characteristics Over Operating Conditions
XCF01S, XCF02S, XCF04S Symbol Description
High-level output voltage for 3.3V outputs High-level output voltage for 2.5V outputs VOH High-level output voltage for 1.8V outputs High-level output voltage for 1.5V outputs Low-level output voltage for 3.3V outputs Low-level output voltage for 2.5V outputs VOL Low-level output voltage for 1.8V outputs Low-level output voltage for 1.5V outputs ICCINT ICCO ICCJ ICCINTS ICCOS ICCJS IILJ Internal voltage supply current, active mode Output driver supply current, active mode JTAG supply current, active mode Internal voltage supply current, standby mode Output driver supply current, standby mode JTAG supply current, standby mode JTAG pins TMS, TDI, and TDO pull-up current IOH = -50 A IOL = 8 mA IOL = 500 A IOL = 50 A 33 MHz TBD TBD TBD TBD VCCJ = max VIN = GND VCCINT = max IIL Input leakage current VIN = GND or VCCINT VCCINT = max IIH Input and output High-Z leakage current VIN = GND or VCCINT VIN = GND f = 1.0 MHz VIN = GND f = 1.0 MHz -10 10 -10 10
XCF08P, XCF16P, XCF32P Test Conditions
IOH = TBD IOH = TBD IOH = TBD IOH = TBD IOL = TBD IOL = TBD IOL = TBD IOL = TBD TBD TBD TBD TBD TBD VCCJ = max VIN = GND VCCINT = max VIN = GND or VCCINT VCCINT = max VIN = GND or VCCINT VIN = GND f = 1.0 MHz VIN = GND f = 1.0 MHz TBD TBD A TBD TBD A
Test Conditions
IOH = -4 mA IOH = -500 A
Min
2.4 VCCO - 0.4 VCCO - 0.4 -
Max
0.4 0.4 0.4 10 TBD TBD 1 TBD TBD 100
Min
TBD TBD TBD TBD -
Max
TBD TBD TBD TBD 10 TBD TBD TBD TBD TBD TBD
Units
V V V V V V V V mA mA mA mA mA mA A
CIN COUT
Input capacitance Output capacitance
-
8 14
-
TBD TBD
pF pF
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Platform Flash In-System Programmable Configuration PROMs
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AC Characteristics Over Operating Conditions
CE
TSCE THCE THOE TLC THC TCYC
OE/RESET
CLK
TCLKO
CLKOUT (optional) BUSY (optional) DATA
TCEC TOEC TOE TCE TCAC TSB THB TOH TCDD TCOH TDF
TOH
CF
EN_EXT_SEL
TSXT
THXT
REV_SEL[1:0]
TSRV
THRV
ds123_22_110403
XCF01S, XCF02S, XCF04S Symbol
OE/RESET to data TOE
XCF08P, XCF16P, XCF32P Min
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
Description
delay (6) when VCCO = 3.3V or 2.5V
Min
0 0 30 67 10 15
Max
10 30 15 30 15 30 25 30 -
Max
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
OE/RESET to data delay (6) when VCCO = 1.8V CE to data delay (5) when VCCO = 3.3V or 2.5V CE to data delay (5) when VCCO = 1.8V
TCE
TCAC
CLK to data delay when VCCO = 3.3V or 2.5V CLK to data delay when VCCO = 3.3V or 2.5V Data hold from CE, OE/RESET, or CLK when VCCO = 3.3V or 2.5V Data hold from CE, OE/RESET, or CLK when VCCO = 1.8V CE or OE/RESET to data float delay (2) when VCCO = 3.3V or 2.5V CE or OE/RESET to data float delay (2) when VCCO = 1.8V Clock period (7) when VCCO = 3.3V or 2.5V Clock period when VCCO = 1.8V CLK Low time (3) when VCCO = 3.3V or 2.5V CLK Low time (3) when VCCO = 1.8V
TOH
TDF
TCYC
TLC
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Platform Flash In-System Programmable Configuration PROMs
XCF01S, XCF02S, XCF04S Symbol
CLK High THC time (3)
XCF08P, XCF16P, XCF32P Min
TBD TBD TBD TBD
Description
when VCCO = 3.3V or 2.5V
Min
10 15 counting) (3) 20 30 250 250 250 250 -
Max
-
Max
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CLK High time (3) when VCCO = 1.8V CE setup time to CLK (guarantees proper when VCCO = 3.3V or 2.5V
TSCE
CE setup time to CLK (guarantees proper counting) (3) when VCCO = 1.8V CE hold time (guarantees counters are reset) (5) when VCCO = 3.3V or 2.5V CE hold time (guarantees counters are reset) (5) when VCCO = 1.8V OE/RESET hold time (guarantees counters are reset) (6) when VCCO = 3.3V or 2.5V OE/RESET hold time (guarantees counters are reset) (6) when VCCO = 1.8V BUSY setup time to CLK when VCCO = 3.3V or 2.5V BUSY setup time to CLK when VCCO = 1.8V BUSY hold time to CLK when VCCO = 3.3V or 2.5V BUSY hold time to CLK when VCCO = 1.8V CLK input to CLKOUT output delay when VCCO = 3.3V or 2.5V CLK input to CLKOUT output delay when VCCO = 1.8V
-
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
THCE
THOE
TSB
THB
TCLKO
TCEC
CE to CLKOUT delay when VCCO = 3.3V or 2.5V CE to CLKOUT delay when VCCO = 1.8V OE/RESET to CLKOUT delay when VCCO = 3.3V or 2.5V OE/RESET to CLKOUT delay when VCCO = 1.8V
TOEC
TCDD
CLKOUT to data delay when VCCO = 3.3V or 2.5V CLKOUT to data delay when VCCO = 1.8V Data hold from CLKOUT when VCCO = 3.3V or 2.5V Data hold from CLKOUT when VCCO = 1.8V EN_EXT_SEL setup time to CF (rising edge) when VCCO = 3.3V or 2.5V EN_EXT_SEL setup time to CF (rising edge) when VCCO = 1.8V EN_EXT_SEL hold time from CF (rising edge) when VCCO = 3.3V or 2.5V EN_EXT_SEL hold time from CF (rising edge) when VCCO = 1.8V REV_SEL setup time to CF (rising edge) when VCCO = 3.3V or 2.5V REV_SEL setup time to CF (rising edge) when VCCO = 1.8V
TCOH
TSXT
THXT
TSRV
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Platform Flash In-System Programmable Configuration PROMs
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XCF01S, XCF02S, XCF04S Symbol Description
REV_SEL hold time from CF (rising edge) when VCCO = 3.3V or 2.5V REV_SEL hold time from CF (rising edge) when VCCO = 1.8V CLKOUT default (fast) frequency TFF CLKOUT default (fast) frequency with compression CLKOUT alternate (slower) frequency TSF CLKOUT alternate (slower) frequency with compression
XCF08P, XCF16P, XCF32P Min
TBD TBD TBD TBD TBD TBD
Min
-
Max
-
Max
TBD TBD TBD TBD TBD TBD
Units
ns ns ns ns ns ns
THRV
Notes: 1. AC test load = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. 5. If THCE High < 2 s, TCE = 2 s. 6. If THOE Low < 2 s, TOE = 2 s. 7. Minimum possible TCYC. Actual TCYC = TCAC + FPGA data setup time. If FPGA data setup time = 15 ns, actual TCYC = 15 ns +15 ns = 30 ns.
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Platform Flash In-System Programmable Configuration PROMs
AC Characteristics Over Operating Conditions When Cascading
OE/RESET
CE
CLK
CLKOUT (optional) DATA Last Bit
TCDF TCODF TOCE TOOE
First Bit
TOCK TCOCE
CEO
ds123_23_102203
XCF01S, XCF02S, XCF04S Symbol
TCDF
XCF08P, XCF16P, XCF32P Min
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
Description
CLK to output float delay (2,3) when VCCO = 2.5V or 3.3V CLK to output float delay (2,3) when VCCO = 1.8V
Min
-
Max
25 35 20 35 20 35 20 35 -
Max
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
Units
ns ns ns ns ns ns ns ns ns ns ns ns
TOCK
CLK to CEO delay (3,5) when VCCO = 2.5V or 3.3V CLK to CEO delay (3,5) when VCCO = 1.8V
TOCE
CE to CEO delay (3) when VCCO = 2.5V or 3.3V CE to CEO delay (3) when VCCO = 1.8V
TOOE
OE/RESET to CEO delay (3) when VCCO = 2.5V or 3.3V OE/RESET to CEO delay (3) when VCCO = 1.8V
TCOCE
CLKOUT to CEO delay when VCCO = 2.5V or 3.3V CLKOUT to CEO delay when VCCO = 1.8V CLKOUT to output float delay when VCCO = 2.5V or 3.3V CLKOUT to output float delay when VCCO = 1.8V
TCODF
Notes: 1. AC test load = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. 5. For cascaded PROMs minimum, TCYC = TOCK + FPGA Data setup time.
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Platform Flash In-System Programmable Configuration PROMs
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Pinouts and Pin Descriptions
The XCFxxS Platform Flash PROM is available in the VO20 package. The XCFxxP Platform Flash PROM is available in the VO48 and FS48 packages. This section includes: *Table 11, XCFxxS Pin Names and Descriptions, page 30 *Figure 17, VO20 Pinout Diagram (Top View) with Pin Names, page 31 *Table 12, XCFxxP Pin Names and Descriptions, page 32 *Figure 18, VO48 Pinout Diagram (Top View) with Pin Names, page 34 *Figure 19, FS48 Pinout Diagram (Top View), page 34 *Table 13, FS48 Pin Number/Name Reference, page 35 Notes: 1. VO20 denotes a 20-pin (TSSOP) Plastic Thin Shrink Small Outline Package 2. VO48 denotes a 48-pin (TSOP) Plastic Thin Small Outline Package. 3. FS48 denotes a 48-pin (TFBGA) Plastic Thin Fine Pitch Ball Grid Array (0.8 mm pitch).
XCFxxS Pinouts and Pin Descriptions
Table 11 provides a list of the pin names and descriptions for the XCFxxS 20-pin VO20 package. Table 11: XCFxxS Pin Names and Descriptions Pin Name
D0 3 CLK 0 20 OE/RESET 19 18 CE 15 Output Enable Data In Data In Data Out Output Enable Data In
Boundary Scan Order
4
Boundary Scan Function
Data Out
Pin Description
D0 is the DATA output pin to provide data for configuring an FPGA in serial mode. The D0 output is set to a high-impedance state during ISPEN (when not clamped). Configuration Clock Input. Each rising edge on the CLK input increments the internal address counter if the CLK input is selected, CE is Low, and OE/RESET is High. Output Enable/Reset (Open-Drain I/O). When Low, this input holds the address counter reset and the DATA output is in a high-impedance state. This is a bidirectional open-drain pin that is held Low while the PROM is reset. Polarity is not programmable. Chip Enable Input. When CE is High, the device is put into low-power standby mode, the address counter is reset, and the DATA pins are put in a high-impedance state. Configuration Pulse (Open-Drain Output). Allows JTAG CONFIG instruction to initiate FPGA configuration without powering down FPGA. This is an open-drain output that is pulsed Low by the JTAG CONFIG command. Chip Enable Output. Chip Enable Output (CEO) is connected to the CE input of the next PROM in the chain. This output is Low when CE is Low and OE/RESET input is High, AND the internal address counter has been incremented beyond its Terminal Count (TC) value. CEO returns to High when OE/RESET goes Low or CE goes High. JTAG Mode Select Input. The state of TMS on the rising edge of TCK determines the state transitions at the Test Access Port (TAP) controller. TMS has an internal 50K resistive pull-up to VCCJ to provide a logic "1" to the device if the pin is not driven.
20-pin TSSOP (VO20)
1
3
8
10
22 CF 21 12 CEO 11
Data Out Output Enable Data Out
7
13
Output Enable
TMS
Mode Select
5
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Platform Flash In-System Programmable Configuration PROMs
Table 11: XCFxxS Pin Names and Descriptions (Continued) Pin Name
TCK
Boundary Scan Order
Boundary Scan Function
Clock
Pin Description
JTAG Clock Input. This pin is the JTAG test clock. It sequences the TAP controller and all the JTAG test and programming electronics. JTAG Serial Data Input. This pin is the serial input to all JTAG instruction and data registers. TDI has an internal 50K resistive pull-up to VCCJ to provide a logic "1" to the device if the pin is not driven. JTAG Serial Data Output. This pin is the serial output for all JTAG instruction and data registers. TDO has an internal 50K resistive pull-up to VCCJ to provide a logic "1" to the system if the pin is not driven. +3.3V Supply. Positive 3.3V supply voltage for internal logic. +3.3V, 2.5V, or 1.8V I/O Supply. Positive 3.3V, 2.5V, or 1.8V supply voltage connected to the output voltage drivers and input buffers. +3.3V, 2.5V, or 1.8V JTAG I/O Supply. Positive 3.3V, 2.5V, or 1.8V supply voltage connected to the TDO output voltage driver and TCK, TMS, and TDI input buffers. Ground Do not connect. (These pins must be left unconnected.)
20-pin TSSOP (VO20)
6
TDI
Data In
4
TDO
Data Out
17
VCCINT VCCO
18 19
VCCJ GND DNC
20 11 2, 9, 12, 14, 15, 16
XCFxxS Pinout Diagram
D0 (DNC) CLK TDI TMS TCK CF OE/RESET (DNC) CE 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCCJ VCCO VCCINT TDO (DNC) (DNC) (DNC) CEO (DNC) GND
ds123_02_102303
VO20 Top View
Figure 17: VO20 Pinout Diagram (Top View) with Pin Names
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XCFxxP Pinouts and Pin Descriptions
Table 12 provides a list of the pin names and descriptions for the XCFxxP 48-pin VO48 and 48-pin FS48 packages. Table 12: XCFxxP Pin Names and Descriptions Boundary Scan Order
28 D0 27 26 D1 25 24 D2 23 22 D3 21 20 D4 19 18 D5 17 16 D6 15 14 D7 13 Output Enable Configuration Clock Input. An internal programmable control bit selects between the internal oscillator and the CLK input pin as the clock source to control the configuration sequence. Each rising edge on the CLK input increments the internal address counter if the CLK input is selected, CE is Low, and OE/RESET is High. Output Enable/Reset (Open-Drain I/O). When Low, this input holds the address counter reset and the DATA and CLKOUT outputs are placed in a high-impedance state. This is a bidirectional open-drain pin that is held Low while the PROM is reset. Polarity is not programmable. Chip Enable Input. When CE is High, the device is put into low-power standby mode, the address counter is reset, and the DATA and CLKOUT outputs are placed in a high-impedance state. Configuration Pulse (Open-Drain I/O). As an output, this pin allows JTAG CONFIG instruction to initiate FPGA configuration without powering down the FPGA. This is an open-drain signal that is pulsed Low by the JTAG CONFIG command. As an input, when Low, this signal enables the device to sample the current design revision selection. 11 A3 Output Enable Data Out 48 A6 Output Enable Data Out 47 A5 Output Enable Data Out Output Enable Data Out Output Enable Data Out Output Enable Data Out D0 is the DATA output pin to provide data for configuring an FPGA in serial mode. D0-D7 are the DATA output pins to provide parallel data for configuring a Xilinx FPGA in SelectMap (parallel) mode. The D0 output is set to a high-impedance state during ISPEN (when not clamped). The D1-D7 outputs are set to a high-impedance state during ISPEN (when not clamped) and when serial mode is selected for configuration. The D1-D7 pins can be left unconnected when the PROM is used in serial mode. 43 C5 32 E5 Output Enable Data Out 29 H5
Pin Name
Boundary Scan Function
Data Out
Pin Description
48-pin TSOP (VO48)
28
48-pin TFBGA (FS48)
H6
33
D5
44
B5
CLK
01
Data In
12
B3
04 OE/RESET 03 02
Data In Data Out Output Enable
CE
00
Data In
13
B4
11 CF 10 09
Data In Data Out Output Enable
6
D1
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DS123 (v2.1) November 18, 2003 Preliminary Product Specification
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Platform Flash In-System Programmable Configuration PROMs
Table 12: XCFxxP Pin Names and Descriptions Boundary Scan Order
06 CEO 05 Output Enable
Pin Name
Boundary Scan Function
Data Out
Pin Description
Chip Enable Output. Chip Enable Output (CEO) is connected to the CE input of the next PROM in the chain. This output is Low when CE is Low and OE/RESET input is High, AND the internal address counter has been incremented beyond its Terminal Count (TC) value. CEO returns to High when OE/RESET goes Low or CE goes High. Enable External Selection Input. When this pin is Low, design revision selection is controlled by the Revision Select pins. When this pin is High, design revision selection is controlled by the internal programmable Revision Select control bits. EN_EXT_SEL has an internal 50K resistive pull-up to VCCO to provide a logic "1" to the device if the pin is not driven. Revision Select[1:0] Inputs. When the EN_EXT_SEL is Low, the Revision Select pins are used to select the design revision to be enabled, overriding the internal programmable Revision Select control bits. The Revision Select[1:0] inputs have an internal 50K resistive pull-up to VCCO to provide a logic "1" to the device if the pins are not driven. Busy Input. The BUSY input is enabled when parallel mode is selected for configuration. When BUSY is High, the internal address counter stops incrementing and the current data remains on the data pins. On the first rising edge of CLK after BUSY transitions from High to Low, the data for the next address is driven on the data pins. When serial mode or decompression is enabled during device programming, the BUSY input is disabled. BUSY has an internal 50K resistive pull-down to GND to provide a logic "0" to the device if the pin is not driven. Configuration Clock Output. An internal Programmable control bit enables the CLKOUT signal which is sourced from either the internal oscillator or the CLK input pin. Each rising edge on the selected clock source increments the internal address counter if data is available, CE is Low, and OE/RESET is High. Output data is available on the rising edge of CLKOUT. CLKOUT remains Low when data is not ready. When CLKOUT is not enabled , the CLKOUT pin is put into a high-impedance state. JTAG Mode Select Input. The state of TMS on the rising edge of TCK determines the state transitions at the Test Access Port (TAP) controller. TMS has an internal 50K resistive pull-up to VCCJ to provide a logic "1" to the device if the pin is not driven. JTAG Clock Input. This pin is the JTAG test clock. It sequences the TAP controller and all the JTAG test and programming electronics. JTAG Serial Data Input. This pin is the serial input to all JTAG instruction and data registers. TDI has an internal 50K resistive pull-up to VCCJ to provide a logic "1" to the device if the pin is not driven.
48-pin TSOP (VO48)
48-pin TFBGA (FS48)
10
D2
EN_EXT_SEL
31
Data In
25
H4
REV_SEL0
30
Data In
26
G3
REV_SEL1
29
Data In
27
G4
BUSY
12
Data In
5
C1
08 CLKOUT 07
Data Out
9
C2
Output Enable
TMS
Mode Select
21
E2
TCK
Clock
20
H3
TDI
Data In
19
G1
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Platform Flash In-System Programmable Configuration PROMs Table 12: XCFxxP Pin Names and Descriptions Boundary Scan Order Boundary Scan Function 48-pin TSOP (VO48) 48-pin TFBGA (FS48)
R
Pin Name
Pin Description
JTAG Serial Data Output. This pin is the serial output for all JTAG instruction and data registers. TDO has an internal 50K resistive pull-up to VCCJ to provide a logic "1" to the system if the pin is not driven. +1.8V Supply. Positive 1.8V supply voltage for internal logic. +3.3V, 2.5V, or 1.8V I/O Supply. Positive 3.3V, 2.5V, or 1.8V supply voltage connected to the output voltage drivers and input buffers. +3.3V, 2.5V, or 1.8V JTAG I/O Supply. Positive 3.3V, 2.5V, or 1.8V supply voltage connected to the TDO output voltage driver and TCK, TMS, and TDI input buffers.
TDO
Data Out
22
E6
VCCINT
4, 15, 34 8, 30, 38, 45
B1, E1, G6 B2, C6, D6, G5
VCCO
VCCJ
24 2, 7, 17, 23, 31, 36, 46 1, 3, 14, 16, 18, 35, 37, 39, 40, 41, 42
H2 A1, A2, B6, F1, F5, F6, H1 A4, C3, C4, D3, D4, E3, E4, F2, F3, F4, G2
GND
Ground
DNC
Do Not Connect. (These pins must be left unconnected.)
XCFxxP Pinout Diagrams
DNC GND DNC VCCINT BUSY CF GND VCCO CLKOUT CEO OE/RESET CLK CE DNC VCCINT DNC GND DNC TDI TCK TMS TDO GND VCCJ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 D7 D6 GND VCCO D5 D4 DNC DNC DNC DNC VCCO DNC GND DNC VCCINT D3 D2 GND VCCO D1 D0 REV_SEL1 REV_SEL0 EN_EXT_SEL
ds123_24_111703
FS48 Top View
1 2 3 4 5 6
VO48 Top View
A B C D E F G H
ds121_01_102303
Figure 18: VO48 Pinout Diagram (Top View) with Pin Names
Figure 19: FS48 Pinout Diagram (Top View)
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DS123 (v2.1) November 18, 2003 Preliminary Product Specification
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Platform Flash In-System Programmable Configuration PROMs
Table 13: FS48 Pin Number/Name Reference Pin Number
A1 A2 A3 A4 A5 A6 B1 B2 B3 B4 B5 B6 C1 C2 C3 C4 C5 C6 D1 D2 D3 D4 D5 D6
Pin Name
GND GND OE/RESET DNC D6 D7 VCCINT VCCO CLK CE D5 GND BUSY CLKOUT DNC DNC D4 VCCO CF CEO DNC DNC D3 VCCO
Pin Number
E1 E2 E3 E4 E5 E6 F1 F2 F3 F4 F5 F6 G1 G2 G3 G4 G5 G6 H1 H2 H3 H4 H5 H6
Pin Name
VCCINT TMS DNC DNC D2 TDO GND DNC DNC DNC GND GND TDI DNC REV_SEL0 REV_SEL1 VCCO VCCINT GND VCCJ TCK EN_EXT_SEL D1 D0
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Platform Flash In-System Programmable Configuration PROMs
R
Ordering Information
XCF04S VO20 C
Device Number XCF01S XCF02S XCF04S Package Type VO20 = 20-pin TSSOP Package Operating Range/Processing C = (TA = -40C to +85C)
XCF32P FS48 C
Device Number XCF08P XCF16P XCF32P Package Type VO48 = 48-pin TSOP Package FS48 = 48-pin TFBGA Package Operating Range/Processing C = (TA = -40C to +85C)
Valid Ordering Combinations
XCF01SVO20 C XCF02SVO20 C XCF04SVO20 C XCF08PVO48 C XCF16PVO48 C XCF32PVO48 C XCF08PFS48 C XCF16PFS48 C XCF32PFS48 C
Marking Information
XCF04S-V
Device Number XCF01S XCF02S XCF04S XCF08P XCF16P XCF32P Package Type V = 20-pin TSSOP Package (VO20) VO48 = 48-pin TSOP Package (VO48) F48 = 48-pin TFBGA Package (FS48) Operating Range/Processing C = (TA = -40C to +85C)
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DS123 (v2.1) November 18, 2003 Preliminary Product Specification
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Platform Flash In-System Programmable Configuration PROMs
Revision History
The following table shows the revision history for this document. Date 04/29/03 06/03/03 11/05/03 11/18/03 Version 1.0 1.1 2.0 2.1 Xilinx Initial Release. Made edits to all pages. Major revision. Pinout corrections as follows: * Table 12: - For VO48 package, removed 38 from VCCINT and added it to VCCO. - For FS48 package, removed pin D6 from VCCINT and added it to VCCO. * Table 13 (FS48 package): - For pin D6, changed name from VCCINT to VCCO. - For pin A4, changed name from GND to DNC. * Figure 18 (VO48 package): For pin 38, changed name from VCCINT to VCCO. Revision
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